COMP124

User software <-> (Kernel <-> Device Drivers) -> (CPU, Memory, Devices)
Buses between CPU, Memory, and Devices

Von Neumann Model

• Input device -> (CPU <-> Memory) -> Output device
• Input device used to load programs & data into memory (Stored program concept)
• CPU fetches program instructions from memory, processes data, generates results
• Results sent to output device

CPU (Central Processing Unit)

• Fetches instructions from memory, executes them
  • Very basic instructions (eg. move value, add two values)
  • Different instruction sets (eg. Apple, AMD, Intel)
  • No standard instruction set or format, but similar operations
• Most common types of instruction set
  • CISC - Complex Instruction Set Computer (eg Intel x86, most desktop/server CPUs)
  • RISC - Reduced Instruction Set Computer (smartphones & small IoT devices)
• Internal activity synchronised by a fast clock
  • Measured in hz

System Bus

• The bus is a collection of wires that allows communication between components on the computer's motherboard
• Without a bus, we'd have to directly connect every component to every other component, which is complicated and expensive (point-to-point system)
• Sender places an item (data) on the bus and receiver takes it off
• The bus can have multiple lines
  • Address lines - used to carry a specific memory address (or device) to be accessed
  • Data lines - carries the actual data to be transferred
  • Control lines - tells the receiver what to do with the data
• Almost all modern computers have multiple interconnected system buses (SATA, PCIe, USB)
• There is a problem of bus contention because only one thing can be on the bus at once

I/O Devices & Interrupts

• Devices include expansion cards that plug into motherboard (eg. graphics)
• some I/O devices/controllers can be built into motherboard
• can have peripherals that plug in eg. keyboard&mouse
• When performing input/output, the CPU needs to know when a device is ready to receive/transmit, and when it has completed a request
• One option is to use polling
  • Periodically check device status
  • Requires CPU to stop what it's doing
  • Wastes time (CPU cycles)
• Modern computer systems use interrupts
  • Device sends a signal to the CPU when it's ready (or finished)
  • Invokes an interrupt handler within the operating system
  • Intercepts the interrupt and decides when the CPU will handle it

Internal Memory

• All programs and data must be converted to binary and loaded into internal memory before being processed (stored program concept)
• Memory:
  • RAM - Random Access Memory (r/w, volatile, main memory)
  • ROM - Read Only Memory (r only, non-volatile, stores boot code)
• The bit length of the system determines how much memory can be moved and manipulated by the CPU in one operation
• Most modern systems are 64bit
• Many embedded microprocessors are 8/16bit
• Its possible to run a 32bit OS on a 64bit system
• Software for 32bit can usually run on 64bit (but not vice versa)

Bit Length & Word Size

• The bit length of the system is related to the word size of variables in our code
  • Size of CPU registers
  • Width of the system bus
• The max unsigned int that can be stored relates to the max memory size (modern memory is *byte addressable)
  • 16bit - word - 64 kilobytes
  • 32bit - dword - 4 gigabytes
  • 64bit - qword - 16 exabytes
• Individual bits are zero-indexed from right to left
  • Bit zero (right-most) is called the least significant bit (lsb)
  • Can also refer to the least significant byte in the same manner

Inside the CPU

• General Purpose Registers, Instruction Register (IR), Instruction Pointer (IP) (same as program counter)
• Control Unit (CU)
• Arithmetic Logic Unit (ALU)
• Memory Management Unit (MMU)
  • MBR (Memory Buffer Register)
  • MAR (Memory Address Register)

CPU Structure

• Control Unit governs CPU activity
• ALU performs bit manipulations & numeric operations
• CU provides ALU with data (operands) and tells it what to do
• CPU has internal registers
  • Access is much faster than storing things in RAM
  • They have unique names and can be general purpose or have a specific use
  • They hold data temporarily while operations are being carried out by the ALU
• The instruction pointer (IP), also known as the program counter (PC) always holds the memory address of the next instruction to be carried out
• The instruction register (IR) holds the instruction currently being executed
• The memory address register (MAR) and memory buffer register (MBR) are used by the CPU to interface with main memory (and are not accessible to the programmer)

Fetch-Execute Cycle

• A program is just a sequence of instructions in successive memory locations

• It will be loaded from disk into a contiguous chunk of memory

• To execute the program, the instruction pointer is set to point to the memory address of the first instruction

• Step 1:

  • Copy address in IP to MAR
  • Issue read request to MMU
  • (Memory access is slow, the CPU can get on with something else while it waits for the memory request to happen)

• Step 2:

  • Increment IP to point to the next instruction

• Step 3:

  • Current instruction arrives from memory into MBR
  • Copy instruction into IR

• Step 4:

  • Decode IR to get the instruction

• Step 5:

  • Fetch any operands (data)

• Step 6:

  • Carry out the instruction (via ALU, etc.)

• Step 7:

  • Go to step 1
    (Steps 5 & 6 may cause further memory access)

Instruction Sets

• The CPU instruction set provides various operations that fall into six broad categories
  • Transfer - moving between memory and registers
  • Arithmetic - simple maths operations
  • Logic - bit manipulations such as AND, OR, NOT, shift, rotate
  • Test - comparing data values and setting status flags
  • Control - jumps and subroutine calls
  • Misc - various helper operations that don't fit into another category
• Code in high level languages needs to be compiled into a sequence of low level instructions for the CPU to understand

Instruction Format

• Each instruction has an opcode that the CPU understands
  • For example, the number 5 might mean add
  • Whenever the CPU sees the number 5 stores in the IR, it knows it needs to perform an addition
• CPU gets further data (operands) from registers and/or main memory (via MMU requests)
• Many instructions have several opcodes because the operands can be encoded in different ways
  • Adding the contents of two registers
  • Adding a value to a register
  • Adding data from a memory location to a register
• The CPU has to do something slightly different to get the data to be added in each scenario, so there are different opcodes for these slightly different instructions

Intel x86 CPU

• The Intel x86 instruction set is 32-bit
  • The 64-bit version is called x64
• A single x86 instruction can be anywhere from 1 to 15 bytes long
  • When the CPU sees the opcode in the IR, it might need to read more data from main memory to fully complete the instruction
  • The fetch-execute example above was simplified to remove these extra steps
  • For COMP124, its assumed that every instruction takes up 4 bytes of memory, for ease, even though this is not the real life case

Addressing Modes

• The mode part of the instruction tells the CPU where the operands are located
  • Immediate - operand value is encoded directly into the instruction (eg. a number)
  • Register - operand value is stored in a register
  • Direct - operand value is in main memory, so the instruction encodes its address
  • Register Indirect - instruction specifies a register that holds the address of the operand in main memory
• A fifth mode (implicit) is used when the instruction doesn't need an operand because it always does the same thing (eg. always manipulates or uses the same register)

Generating Instructions

• A compiler turns high level code into a sequence of bytes that represents opcodes and operands in the CPU's instruction set